In a semiconductor device manufacturing process, a desired device is manufactured by repetitively performing various processes such as film formation, etching and the like on a semiconductor wafer. Recently, in order to meet the demands for a high-speed semiconductor device, wiring pattern miniaturization and high-integration, it has been required to realize low resistance of wiring (high conductivity) and high electromigration tolerance.
Accordingly, Cu having high electromigration tolerance and higher conductivity (lower resistance) than Al or W has been used as a wiring material.
As for the Cu wiring forming method, there is suggested a technique for forming a barrier film formed of Ta, Ti, TaN, TiN or the like on an entire interlayer insulating film having a recess such as a trench or a hole by plasma sputtering as PVD (Physical Vapor Deposition), forming a Cu seed layer on the barrier film by plasma sputtering, filling a trench or a hole by performing Cu plating, and removing a residual Cu thin film or a residual barrier film from the wafer surface by CMP (Chemical Mechanical Polishing) (see, e.g., Patent Document 1).
However, as the current density is increased along with the miniaturization of the design rules of semiconductor devices, sufficient electromigration tolerance is not obtained even by using Cu as the wiring material. Therefore, a technique is examined for improving the electromigration tolerance of the Cu wiring.
As for such technique, there is suggested a technique for improving adhesivity between Cu and a dielectric cap (SiCN cap) formed thereon by concentrating an alloy content such as Mn, Al or the like between the Cu wiring and the dielectric cap by using a Cu alloy such as Cu—Mn, Cu—Al or the like as a seed layer, instead of the Cu seed layer (see, e.g., Non-Patent Document 1) or a technique for improving adhesivity between Cu and the dielectric cap by selectively forming a metal cap on a surface of Cu wiring (see, e.g., Patent Documents 2 to 4).